EDN

Low Power SRAM Design [Cadence ICFB, Synopsys DC, 0.12μmCMOS, Hspice]

Designed an 8-Kbit SRAM using sleep transistors to reduce power dissipation. 130nm technology is used to design SRAM cells and HSPICE simulations are used to determine the optimal number and sizes of ...
EDN

The ultra-low-power SRAM IP targets IoT, wearable SoCs

The ultra-low-power memory specialist sureCore is recruiting engineers having 10 years or more experience in memory design. Its embedded SRAM IP targets system-on-chip (SoC) designs that serve ...