SiFive has announced a partnership with Nvidia to integrate Nvidia’s NVLink Fusion interconnect technology into its ...

SiFive, which makes blueprints for parts of complex chips, said on Thursday it will become the first maker of RISC-V chip ...

Bolt Graphics is pressing ahead with its plan to challenge Nvidia and AMD by building a graphics processor around a RISC-V ...

NASA’s future missions face sabotage risks from China’s tech strategy. Leaders must act now—or risk losing the space race for ...

Tenstorrent, under Jim Keller, cut 7.5% of its staff to boost teamwork, launched the Ascalon RISC-V CPU in China for AI and HPC markets, and is partnering with CoreLab and former Arm China CEO Allen ...

The RISC-V Summit North America, held on 22-23 October 2025 in Santa Clara, California, showcased the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems ...

The RISC-V Reference SoC Tapeout Program is a comprehensive 20-week initiative designed to provide hands-on experience in complete chip development - from RTL design to actual silicon fabrication.

Once a hyperscaler or a cloud builder gets big enough, it can afford to design custom compute engines that more precisely match its needs. It is not clear that the companies that make custom CPUs and ...

Big quote: Linus Torvalds, the founder and lead developer of the Linux kernel, firmly rejected a code contribution intended to enhance RISC-V architecture support in the upcoming Linux 6.17 release.

Unlock the full InfoQ experience by logging in! Stay updated with your favorite authors and topics, engage with content, and download exclusive resources. Vivek Yadav, an engineering manager from ...